1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a protection circuit for preventing an electrostatic damage in an integrated circuit.
2. Description of the Related Art
In recent years, the miniaturization of device elements in a semiconductor integrated circuit has been greatly advanced. The minimum size of device elements has reached a so-called submicron level, i.e., 1 .mu.m or less. With the miniaturization of the device elements, in a MOS transistor, the gate oxide film has been made very thin. Because of this, the breakdown voltage of the gate oxide film is decreased, leading to a decrease in the resistance to electrostatic damage. In order to prevent the electrostatic damage, a protection circuit for preventing the electrostatic damage is provided in the vicinity of the pad.
Hereinafter, a conventional protection circuit for preventing an electrostatic damage will be described with reference to the drawings.
FIG. 17 shows an example of an input/output circuit equipped with a conventional protection circuit for preventing an electrostatic damage. In FIG. 17, an input/output terminal 1 is connected to each drain of a p-channel protection transistor 2, an n-channel protection transistor 3, a p-channel output transistor 4, and an n-channel output transistor 5. The input/output terminal 1 is further connected to an internal circuit 7 through an input protection resistor 6. A source and a gate of the p-channel protection transistor 2 are connected to a V.sub.DD supply terminal, and a source and a gate of the n-channel protection transistor 3 are connected to a ground terminal. A source and a gate of the p-channel output transistor 4 are connected to the V.sub.DD supply terminal and an internal circuit 8, respectively. A source and a gate of the n-channel output transistor 5 are connected to the ground terminal and an internal circuit 9, respectively. In the input/output circuit with such a structure, in a case where a surge voltage is applied between the input/output terminal and the ground terminal, the surge voltage is reduced through the n-channel protection transistor 3 which is in a conductive state. Likewise, in a case where a surge voltage is applied between the input/output terminal 1 and the V.sub.DD supply terminal, the surge voltage is reduced through the p-channel protection transistor 2 which is in a conductive state. In addition, the input protection resistor 6 protects the internal circuit 7 by attenuating a surge voltage.
Another example of an input/output circuit equipped with a conventional protection circuit for protecting electrostatic damage is shown in FIG. 19. In FIG. 19, an input/output terminal 49 is connected to each drain of a p-channel protection transistor 10, an n-channel protection transistor 11, a p-channel transfer gate transistor 12, and an n-channel transfer gate transistor 13. Each source of the p-channel transfer gate transistor 12 and the n-channel transfer gate transistor 13 is connected to a capacitor 14 of an internal circuit element (not shown). In addition, a source and a gate of the p-channel protection transistor 10 are connected to a V.sub.DD supply terminal, a source and a gate of the n-channel protection transistor 11 are connected to a ground terminal. A gate of the p-channel transfer gate transistor 12 is connected to an internal circuit 15, and a gate of the n-channel transfer gate transistor 13 is connected to an internal circuit 16. In the input/output circuit with such a structure, in a case where a surge voltage is applied between the input/output terminal 49 and the ground terminal, the surge voltage is discharged through the n-channel protection transistor 11. Likewise, in a case where a surge voltage is applied between the input/output terminal 49 and the V.sub.DD supply terminal, the surge voltage is discharged through the p-channel protection transistor 10.
However, in the above-mentioned structure, there are the following problems:
As shown in FIG. 18, in a case where a surge voltage which is negative with respect to the V.sub.DD supply terminal is applied to the input/output terminal 1 under the condition that the ground terminal is open, the p-channel protection transistor 2 starts discharging. During this time, a high voltage is applied to the gate oxide film of the n-channel output transistor 5, since the gate of the n-channel output transistor 5 is connected to the V.sub.DD supply terminal through a p.sup.+ -drain and an n-well of a p-channel MOS transistor in the internal circuit 9. Since the voltage across a PN junction of the drain of the p-channel protection transistor 2 is clamped to be a certain voltage (discharge voltage), when the resistance of the drain (p-type diffusion) of the p-channel protection transistor 2 is relatively high, the voltage on the input/output terminal 1 cannot be readily decreased and the strong surge stress is applied to the gate oxide film of the n-channel output transistor 5. When the gate oxide film of the n-channel output transistor 5 is made thin along with the miniaturization of the device elements, the gate oxide film of the n-channel output transistor 5 is likely to break down due to the high voltage. FIG. 21 shows the state in which the gate oxide film and the gate electrode (polycrystalline silicon) of the n-channel output transistor 5 are broken down. In a case where a surge voltage which is positive with respect to the ground terminal is applied to the input/output terminal 1 under the condition that the V.sub.DD supply terminal is open, the gate oxide film of the p-channel output transistor 4 will be broken down.
As shown in FIG. 20, the same damage as that caused in the n-channel output transistor 5 in FIG. 18 is caused in the n-channel transfer gate transistor 13.